X28VC256

14

CE Controlled Write Cycle

3869 FHD F07

Page Write Cycle

3869 FHD F08

Notes: (8) Between successive byte writes within a page write operation,

OE can be strobed LOW: e.g. this can be done with CE and WE

HIGH to fetch data from another memory device within the system for the next write; or with

WE HIGH and CE LOW effectively

performing a polling operation.

(9) The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform

to either the

CE or WE controlled write cycle timing.

ADDRESS

tAS

tWC

tAH

tOES

tCS

tDS

tDH

tCH

CE

WE

OE

DATA IN

DATA OUT

HIGH Z

DATA VALID

tCW

tOEH

WE

OE

(8)

BYTE 0

BYTE 1

BYTE 2

BYTE n

BYTE n+1

BYTE n+2

tWP

tWPH

tBLC

tWC

CE

ADDRESS*

(9)

I/O

*For each successive write within the page write operation, A7–A14 should be the same or

writes to an unknown address could occur.

LAST BYTE