IP4778CZ38_2

© NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 02 — 12 February 2009

14 of 26

NXP Semiconductors

IP4778CZ38

HDMI ESD protection, DDC buffering and hot plug control

10.3 Hot Plug driver circuit

The IP4778CZ38 includes a Hot Plug driver circuit that simplifies the Hot Plug application.

The circuit can be connected directly to GPIO pins.

The Hot Plug control input is actively pulled LOW to ensure that at system standby or

startup, the Hot Plug signal is HIGH even if a GPIO pin is in a 3-state condition.

For correct CEC handling, it is essential that the Hot Plug signal is at HIGH-level in

Standby mode. The HDMI source requires a Hot Plug signal so that it can read out the

EDID information to initiate a proper startup CEC sequence.

10.4 CEC

The CEC signal can generate distortions caused by signal ringing in a 1 kHz domain. The

CEC slew rate limiter ensures that a signal does not ring independently of the CEC slave

that is releasing the signal.

A MOSFET transistor implements the backdrive protection which blocks signals during a

power-down state.

The slew rate of the CEC-bus is controlled by a slew rate that is defined independently of

the load (ohmic and capacitive) at the CEC-bus.

(1) Dotted line indicates effect without slew rate accelerator.

Fig 8.

DDC output waveform

001aag042

(1)

(1)

5.0 V

Fig 9.

Hot Plug driver circuit

001aag043

10

µA

HOT_PLUG_DET_IN

HOT_PLUG_DET_OUT

TMDS_BIAS