PCIMX258CJM4A datasheet(65/144 Pages) FREESCALE

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i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 3

Freescale Semiconductor

Figure 32. DDR2 SDRAM Write Cycle Timing Diagram

Table 50. DDR2 SDRAM Write Cycle Parameter Table

Parameter

Symbol

DDR2-400

Unit

Min.

Max.

DDR17

DQ & DQM setup time to DQS (single-ended strobe)1

1 These values are for a DQ/DM slew rate of 1 V/ns and a DQS slew rate of 1 V/ns. For additional values use Table 51, “DtDS1,

DtDH1 Derating Values for DDR2-400, DDR2-533.”

tDS1(base)

0.025

—

DDR18

DQ & DQM hold time to DQS (single-ended strobe)1

tDH1(base)

0.025

—

DDR19

Write cycle DQS falling edge to SDCLK output setup time

tDSS

0.2

—

tCK

DDR20

Write cycle DQS falling edge to SDCLK output hold time

tDSH

0.2

—

tCK

DDR21

DQS latching rising transitions to associated clock edges

tDQSS

-0.25

0.25

tCK

DDR22

DQS high-level width

tDQSH

0.35

—

tCK

DDR23

DQS low-level width

tDQSL

0.35

—

tCK

Table 51.

ΔtDS1, ΔtDH1 Derating Values for DDR2-400, DDR2-5331,2,3

DQS Single-Ended Slew Rate

2.0 V/ns

1.5 V/ns

1.0 V/ns

0.9 V/ns

0.8 V/ns

0.7 V/ns

0.6 V/ns

0.5 Vns

0.4 V/ns

ΔtD

SDCLK

SDCLK_B

DQS (output)

DQ (output)

DQM (output)

Data

DDR17

DDR18

DDR19

DDR20

DDR21

DDR23

DDR22

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