HT86B10 datasheet(64/83 Pages) HOLTEK

64 / 83 page

HT86BXX/HT86BRXX

Rev. 1.80

March 12, 2010

Bit Operations

The ability to provide single bit operations on Data Mem-

ory is an extremely flexible feature of all Holtek

microcontrollers. This feature is especially useful for

output port bit programming where individual bits or port

pins can be directly set high or low using either the

²SET

[m].i

² or ²CLR [m].i² instructions respectively. The fea-

ture removes the need for programmers to first read the

8-bit output port, manipulate the input data to ensure

that other bits are not changed and then output the port

with the correct new data. This read-modify-write pro-

cess is taken care of automatically when these bit oper-

ation instructions are used.

Table Read Operations

Data storage is normally implemented by using regis-

ters. However, when working with large amounts of

fixed data, the volume involved often makes it inconve-

nient to store the fixed data in the Data Memory. To over-

come this problem, Holtek microcontrollers allow an

area of Program Memory to be setup as a table where

data can be directly stored. A set of easy to use instruc-

tions provides the means by which this fixed data can be

referenced and retrieved from the Program Memory.

Other Operations

In addition to the above functional instructions, a range

of other instructions also exist such as the

²HALT² in-

struction for Power-down operations and instructions to

control the operation of the Watchdog Timer for reliable

program operations under extreme electric or electro-

magnetic environments. For their relevant operations,

refer to the functional related sections.

Instruction Set Summary

The following table depicts a summary of the instruction

set categorised according to function and can be con-

sulted as a basic instruction reference using the follow-

ing listed conventions.

Table conventions:

x: Bits immediate data

m: Data Memory address

A: Accumulator

i: 0~7 number of bits

addr: Program memory address

Mnemonic

Description

Cycles

Flag Affected

Arithmetic

ADD A,[m]

ADDM A,[m]

ADD A,x

ADC A,[m]

ADCM A,[m]

SUB A,x

SUB A,[m]

SUBM A,[m]

SBC A,[m]

SBCM A,[m]

DAA [m]

Add Data Memory to ACC

Add ACC to Data Memory

Add immediate data to ACC

Add Data Memory to ACC with Carry

Add ACC to Data memory with Carry

Subtract immediate data from the ACC

Subtract Data Memory from ACC

Subtract Data Memory from ACC with result in Data Memory

Subtract Data Memory from ACC with Carry

Subtract Data Memory from ACC with Carry, result in Data Memory

Decimal adjust ACC for Addition with result in Data Memory

Note

Z, C, AC, OV

Logic Operation

AND A,[m]

OR A,[m]

XOR A,[m]

ANDM A,[m]

ORM A,[m]

XORM A,[m]

AND A,x

OR A,x

XOR A,x

CPL [m]

CPLA [m]

Logical AND Data Memory to ACC

Logical OR Data Memory to ACC

Logical XOR Data Memory to ACC

Logical AND ACC to Data Memory

Logical OR ACC to Data Memory

Logical XOR ACC to Data Memory

Logical AND immediate Data to ACC

Logical OR immediate Data to ACC

Logical XOR immediate Data to ACC

Complement Data Memory

Complement Data Memory with result in ACC

Note

Increment & Decrement

INCA [m]

INC [m]

DECA [m]

DEC [m]

Increment Data Memory with result in ACC

Increment Data Memory

Decrement Data Memory with result in ACC

Decrement Data Memory

Note

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