Selection Guide

The following table summarises the main features of each device.

Part No.

VDD

Program

Memory

Data

Memory

General

I/O

Timer

CPT

Detector

DTMF

Generator

DTMF

Receiver

Stack

Package

HT95R43

2.2V~

5.5V

4K

´16

1152

´828

16-bit

´2

ÖÖ

Ö

8

64LQFP

HT95R44

2.2V~

5.5V

8K

´16

2112

´828

16-bit

´2

ÖÖ

Ö

8

64LQFP

Block Diagram

The following block diagram illustrates the dual-chip structure of the devices, where an individual MCU and CPT Detec-

tor devices are combined into a single package.

HT95R43/HT95R44

Rev. 1.00

2

March 31, 2010

H T 9 0 2 0 B

V S S

V S S 4

I / O P o r t s

T M R n P i n s

I N T P i n s

A n a l o g I n p u t s

O S C P i n s

S i g n a l O u t p u t s

R E S

C P T E N

C P T X 1

C P T X 2

C P T E N V

C P T V R E F

C P T S I N

V D D

V D D 4

H T 9 5 R 3 3

H T 9 5 R 3 4

V D D

V D D

G N D

V S S

Internal Chip Interconnection Diagram

D T M F

G e n e r a t o r

S t a c k

O T P

P r o g r a m

M e m o r y

D a t a

M e m o r y

W a t c h d o g

T i m e r

W a t c h d o g

T i m e r O s c i l l a t o r

8 - b i t

R I S C

M C U

C o r e

R e s e t

C i r c u i t

I n t e r r u p t

C o n t r o l l e r

3 2 7 6 8 H z

C r y s t a l

O s c i l l a t o r

P L L

P r o g r a m m a b l e

F r e q u e n c y

G e n e r a t o r

1 6 - b i t

T i m e r s

I / O

P o r t s

D T M F

R e c e i v e r

C P T

D e t e c t o r