HT86B40 datasheet(30/83 Pages) HOLTEK

30 / 83 page

HT86BXX/HT86BRXX

Rev. 1.80

March 12, 2010

Because the TBLH register is a read-only register and

cannot be restored, care should be taken to ensure its

protection if both the main routine and Interrupt Service

Routine use table read instructions. If using the table

read instructions, the Interrupt Service Routines may

change the value of the TBLH and subsequently cause

errors if used again by the main routine. As a rule it is

recommended that simultaneous use of the table read

instructions should be avoided. However, in situations

where simultaneous use cannot be avoided, the inter-

rupts should be disabled prior to the execution of any

main routine table-read instructions. Note that all table

related instructions require two instruction cycles to

complete their operation.

Instruction

Table Location

*12

*11

*10

TABRDC [m]

P12

P11

P10

TABRDL [m]

11111

Table Location

Note:

*12~*0: Current Program ROM table

P12~P8: Write P12~P8 to TBHP pointer register

@7~@0: Write @7~@0 to TBLP pointer register

For the HT86B03, the table address location is 12-bits, that is from bit 0 to bit 11.

Data Memory

The Data Memory is a volatile area of 8-bit wide RAM in-

ternal memory and is the location where temporary in-

formation is stored. Divided into two sections, the first of

these is an area of RAM where special function registers

are located. These registers have fixed locations and

are necessary for correct operation of the device. Many

of these registers can be read from and written to di-

rectly under program control, however, some remain

protected from user manipulation. The second area of

RAM Data Memory is reserved for general purpose use.

All locations within this area are read and write accessi-

ble under program control.

Organization

The Data Memory is subdivided into two banks, known

as Bank 0 and Bank 1, all of which are implemented in

8-bit wide RAM. Most of the RAM Data Memory is lo-

cated in Bank 0 which is also subdivided into two sec-

tions, the Special Purpose Data Memory and the

General Purpose Data Memory. The length of these

sections is dictated by the type of microcontroller cho-

sen. The start address of the RAM Data Memory for all

devices is the address

²00H², and the last Data Memory

address is

²FFH². Registers which are common to all

microcontrollers, such as ACC, PCL, etc., have the

same Data Memory address.

General Purpose Data Memory

All microcontroller programs require an area of

read/write memory where temporary data can be stored

and retrieved for use later. It is this area of RAM memory

that is known as General Purpose Data Memory. This

area of Data Memory is fully accessible by the user pro-

gram for both read and write operations. By using the

S p e c i a l P u r p o s e

D a t a M e m o r y

0 0 H

F F H

2 D H

G e n e r a l P u r p o s e

D a t a M e m o r y

( 1 9 2 B y t e s )

H T 8 6 B 0 3

H T 8 6 B 1 0 / H T 8 6 B R 1 0

H T 8 6 B 2 0 / H T 8 6 B 3 0

H T 8 6 B R 3 0

: U n k n o w n

0 0 H

4 0 H

F F H

3 9 H

S p e c i a l P u r p o s e

D a t a M e m o r y

G e n e r a l P u r p o s e

D a t a M e m o r y

( 1 9 2 B y t e s )

4 0 H

H T 8 6 B 4 0 / H T 8 6 B 5 0

H T 8 6 B 6 0 / H T 8 6 B R 6 0

H T 8 6 B 7 0 / H T 8 6 B 8 0

H T 8 6 B 9 0

B a n k 1

M e m o r y

4 0 H

F F H

B a n k 0

RAM Data Memory Structure

- Bank 0, Bank1

Note: Most of the RAM Data Memory bits can be directly manipulated using the

²SET [m].i² and ²CLR [m].i² instruc-

tions with the exception of a few dedicated bits. The RAM Data Memory can also be accessed through the

Memory Pointer registers MP0 and MP1.

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