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MPC8308 データシート(PDF) 17 Page - Freescale Semiconductor, Inc |
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MPC8308 データシート(HTML) 17 Page - Freescale Semiconductor, Inc |
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17 / 88 page  MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 0 Freescale Semiconductor 17 Ethernet: Three-Speed Ethernet, MII Management 8.2.1.1 MII Transmit AC Timing Specifications Table 23 provides the MII transmit AC timing specifications. Figure 8 shows the MII transmit AC timing diagram. Figure 8. MII Transmit AC Timing Diagram 8.2.1.2 MII Receive AC Timing Specifications Table 24 provides the MII receive AC timing specifications. Table 23. MII Transmit AC Timing Specifications At recommended operating conditions with LVDDA/LVDDB /NVDD of 3.3 V ± 0.3V. Parameter/Condition Symbol 1 Min Typ Max Unit TX_CLK clock period 10 Mbps tMTX — 400 — ns TX_CLK clock period 100 Mbps tMTX —40— ns TX_CLK duty cycle tMTXH/tMTX 35 — 65 % TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay tMTKHDX 15 15 ns TX_CLK data clock rise VIL(min) to VIH(max) tMTXR 1.0 — 4.0 ns TX_CLK data clock fall VIH(max) to VIL(min) tMTXF 1.0 — 4.0 ns Note: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII transmit timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in general, the clock reference symbol representation is based on two to three letters representing the clock of a particular functional. For example, the subscript of tMTX represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). Table 24. MII Receive AC Timing Specifications At recommended operating conditions with LVDD /NVDD of 3.3 V ± 0.3V. Parameter/Condition Symbol 1 Min Typ Max Unit RX_CLK clock period 10 Mbps tMRX — 400 — ns RX_CLK clock period 100 Mbps tMRX —40— ns RX_CLK duty cycle tMRXH/tMRX 35 — 65 % RXD[3:0], RX_DV, RX_ER setup time to RX_CLK tMRDVKH 10.0 — — ns TX_CLK TXD[3:0] tMTKHDX tMTX tMTXH tMTXR tMTXF TX_EN TX_ER |
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