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24LC32AXT-E/P データシート(PDF) 3 Page - Microchip Technology |
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24LC32AXT-E/P データシート(HTML) 3 Page - Microchip Technology |
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3 / 42 page  2010 Microchip Technology Inc. DS21713L-page 3 24AA32A/24LC32A TABLE 1-2: AC CHARACTERISTICS AC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C, VCC = +1.7V to +5.5V Automotive (E): TA = -40°C to +125°C, VCC = +2.5V to +5.5V Param. No. Symbol Characteristic Min. Max. Units Conditions 1FCLK Clock Frequency — — 400 100 kHz 2.5V VCC 5.5V 1.7V VCC 2.5V (24AA32A) 2 THIGH Clock High Time 600 4000 — — ns 2.5V VCC 5.5V 1.7V VCC 2.5V (24AA32A) 3TLOW Clock Low Time 1300 4700 — — ns 2.5V VCC 5.5V 1.7V VCC 2.5V (24AA32A) 4TR SDA and SCL Rise Time (Note 1) — — 300 1000 ns 2.5V VCC 5.5V 1.7V VCC 2.5V (24AA32A) 5TF SDA and SCL Fall Time — 300 ns (Note 1) 6THD:STA Start Condition Hold Time 600 4000 — — ns 2.5V VCC 5.5V 1.7V VCC 2.5V (24AA32A) 7TSU:STA Start Condition Setup Time 600 4700 — — ns 2.5V VCC 5.5V 1.7V VCC 2.5V (24AA32A) 8THD:DAT Data Input Hold Time 0 — ns (Note 2) 9TSU:DAT Data Input Setup Time 100 250 — — ns 2.5V VCC 5.5V 1.7V VCC 2.5V (24AA32A) 10 TSU:STO Stop Condition Setup Time 600 4000 — — ns 2.5V VCC 5.5V 1.7V VCC 2.5V (24AA32A) 11 TSU:WP WP Setup Time 600 4000 — — ns 2.5V VCC 5.5V 1.7V VCC < 2.5V (24AA32A) 12 THD:WP WP Hold Time 1300 4700 — — ns 2.5V VCC 5.5V 1.7V VCC < 2.5V (24AA32A) 13 TAA Output Valid from Clock (Note 2) — — 900 3500 ns 2.5V VCC 5.5V 1.7V VCC 2.5V (24AA32A) 14 TBUF Bus free time: Time the bus must be free before a new transmission can start 1300 4700 — — ns 2.5V VCC 5.5V 1.7V VCC 2.5V (24AA32A) 15 TOF Output Fall Time from VIH Minimum to VIL Maximum 20+0.1CB — 250 250 ns 2.5V VCC 5.5V 1.7V VCC 2.5V (24AA32A) 16 TSP Input Filter Spike Suppression (SDA and SCL pins) —50 ns (Notes 1 and 3) 17 TWC Write Cycle Time (byte or page) —5 ms — 18 — Endurance 1M — cycles Page mode, 25°C, VCC 5.5V (Note 4) Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained on Microchip’s web site at www.microchip.com. |
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