Obsolete

Product(s)

- Obsolete

Product(s)

TSA1002

4/20

ELECTRICAL CHARACTERISTICS

AVCC = DVCC = VCCB = 2.5V, Fs= 40Msps,Fin= 1MHz, Vin@ -1.0dBFS, VREFM= 0V

Tamb = 25 C (unless otherwise specified)

TIMING CHARACTERISTICS

TIMING DIAGRAM

Symbol

Parameter

Test conditions

Min

Typ

Max

Unit

FS

Sampling Frequency

0.5

50

Msps

DC

Clock Duty Cycle

40

50

60

%

TC1

Clock pulse width (high)

9

10

ns

TC2

Clock pulse width (low)

9

10

ns

Tod

Data Output Delay (Fall of Clock

to Data Valid)

10pF load capacitance

5ns

Tpd

Data Pipeline delay

5.5

cycles

Ton

Falling edge of OEB to digital

output valid data

1ns

Toff

Rising edge of OEB to digital

output tri-state

1ns

N-1

N

N+1

N+6

N+7

N+2

N+3

N+8

N+1

N+2

N-1

N-2

N-3

N-4

N-5

N-6

N-7

CLK

DR

Tod

Ton

Toff

Tpd + Tod

HZ state

DATA

OUT

OEB