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ADS58C48IPFPR データシート(PDF) 9 Page - Texas Instruments

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部品番号 ADS58C48IPFPR
部品情報  Quad Channel IF Receiver with SNRBoost 3G
PDF  70 Pages
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メーカー  TI [Texas Instruments]
ホームページ  http://www.ti.com
Logo TI - Texas Instruments

ADS58C48IPFPR データシート(HTML) 9 Page - Texas Instruments

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ADS58C48
www.ti.com
SLAS689 – MAY 2010
TIMING CHARACTERISTICS – LVDS AND CMOS MODES
(1) (continued)
Typical values are at 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, sampling frequency = 200 MSPS, sine wave input clock, CLOAD =
5 pF
(2), R
LOAD = 100 Ω
(3), unless otherwise noted.
MIN and MAX values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 1.8 V, DRVDD = 1.7 V to
1.9 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tCLKRISE,
Output clock rise time
Rise time measured from 20% to 80% of DRVDD
0.6
ns
tCLKFALL
Output clock fall time
Fall time measured from 80% to 20% of DRVDD
1 ≤ Sampling frequency ≤ 150 MSPS
Table 2. LVDS Timings Across Sampling Frequencies
SETUP TIME, ns
HOLD TIME, ns
SAMPLING FREQUENCY, MSPS
MIN
TYP
MAX
MIN
TYP
MAX
185
0.7
1.30
0.35
0.70
170
0.9
1.55
0.35
0.70
150
1.2
1.9
0.35
0.70
125
1.9
2.6
0.35
0.70
Table 3. CMOS Timings Across Sampling Frequencies
TIMINGS SPECIFIED WITH RESPECT TO INPUT CLOCK
SAMPLING FREQUENCY
tSTART, ns
DATA VALID TIME, ns
MSPS
MIN
TYP
MAX
MIN
TYP
MAX
185
–1.4
3.6
4.2
170
–2.8
4.2
4.7
150
–4.6
4.8
5.4
125
1.0
6.2
6.8
TIMINGS SPECIFIED WITH RESPECT TO CLKOUT
SAMPLING FREQUENCY
tPDI, CLOCK PROPAGATION
SETUP TIME, ns
HOLD TIME, ns
MSPS
DELAY, ns(1)
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
150
2.0
2.8
2.0
2.8
125
2.6
3.5
2.6
3.5
80
4.8
5.8
4.8
5.8
80 to 150
5
6.5
8
(1)
At higher frequencies, tPDI is greater than one clock period and overall latency = ADC latency + 1.
Copyright © 2010, Texas Instruments Incorporated
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