R

P

SDA

SCL

Master

Slave

CDCE913

CDCEL913

C

BUS

C

BUS

R

P

CDCE913

CDCEL913

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SCAS849E – JUNE 2007 – REVISED MARCH 2010

SDA/SCL HARDWARE INTERFACE

Figure 13 shows how the CDCE913/CDCEL913 clock synthesizer is connected to the SDA/SCL serial interface

bus. Multiple devices can be connected to the bus but the speed may need to be reduced (400 kHz is the

maximum) if many devices are connected.

devices. The recommended pullup value is 4.7 k

Ω. It must meet the minimum sink current of 3 mA at

Figure 13. SDA / SCL Hardware Interface

SDA/SCL CONFIGURATION REGISTERS

The clock input, control pins, PLLs, and output stages are user configurable. The following tables and

explanations describe the programmable functions of the CDCE913/CDCEL913. All settings can be manually

written into the device via the SDA/SCL bus or easily programmed by using the TI Pro-Clock™ software. TI

Pro-Clock™ software allows the user to quickly make all settings and automatically calculates the values for

optimized performance at lowest jitter.

Table 7. SDA/SCL Registers

Address Offset

Register Description

Table

00h

Generic Configuration Register

Table 9

10h

PLL1 Configuration Register

Table 10

The grey-highlighted bits, described in the Configuration Registers tables in the following pages, belong to the

Control Terminal Register. The user can predefine up to eight different control settings. These settings then can

be selected by the external control pins, S0, S1, and S2. See the Control Terminal Configuration section.

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Product Folder Link(s): CDCE913 CDCEL913