KM416RD8AS-RBM80 datasheet(32/64 Pages) SAMSUNG

32 / 64 page

Page 29

KM416RD8AS

Direct RDRAM™

Rev. 0.9 July 1999

Target

Initialization (continued)

In essence, the controller must read all the read-only config-

uration registers of all RDRAMs, it must process this infor-

mation, and then it must write all the read-write registers to

place the RDRAMs into the proper operating mode. The

most important of these read-write registers are DEVID (the

device address for memory transactions) and TRDLY

(which sets the delay value for memory read data).

During the initialization process, it is necessary for the

controller to perform 128 current control operations

(3xCAL, 1xCAL/SAM) and one temperature calibrate oper-

ation (TCEN/TCAL) after reset or after powerdown (PDN)

exit.

There are two classes of 128Mbit RDRAM. They are distin-

guished by the “S28IECO” bit in the SPD. The behavior of

the RDRAM at initialization is slightly different for the two

types:

S28IECO=0: Upon powerup the device enters ATTN state.

The serial operations SETR, CLRR, and SETF are

performed without requiring a SDEVID match of the SBC

bit (broadcast) to be set.

S28IECO=1: Upon powerup the device enters PDN state.

The serial operations SETR, CLRR, and SETF require a

SDEVID match.

See the document detailing the reference initialization proce-

dure for more information on how to handle this in a system.

After the step of equalizing the total read delay of each

RDRAM has been completed (i.e. after the TCDLY0 and

TCDLY1 fields have been written for the final time), a

single final memory read transaction should be made to each

RDRAM in order to ensure that the output pipeline stages

have been cleared.

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