K6R1016V1D

CMOS SRAM

Revision 3.0

- 7 -

June 2002

for AT&T

NOTES(READ CYCLE)

1. WE is high for read cycle.

2. All read cycle timing is referenced from the last valid address to the first transition address.

device.

5. Transition is measured

±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.

7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.

Address

CS

UB, LB

WE

Data in

Data out

High-Z

High-Z

Valid Data

OE

Valid Data

High-Z

CS

Address

UB, LB

OE

Data out

50%

50%

Current