K6R1016V1D

CMOS SRAM

Revision 3.0

- 6 -

June 2002

for AT&T

Address

Data Out

Previous Valid Data

Valid Data

TIMING DIAGRAMS

READ CYCLE*

* The above parameters are also guaranteed at industrial temperature range.

Parameter

Symbol

K6R1016V1D-08

K6R1016V1D-10

Unit

Min

Max

Min

Max

Read Cycle Time

8

-

10

-

ns

Address Access Time

-

8

-

10

ns

Chip Select to Output

-

8

-

10

ns

Output Enable to Valid Output

-

4

-

5

ns

UB, LB Access Time

-

4

-

5

ns

Chip Enable to Low-Z Output

3

-

3

-

ns

Output Enable to Low-Z Output

0

-

0

-

ns

UB, LB Enable to Low-Z Output

0

-

0

-

ns

Chip Disable to High-Z Output

0

4

0

5

ns

Output Disable to High-Z Output

0

4

0

5

ns

UB, LB Disable to High-Z Output

0

4

0

5

ns

Output Hold from Address Change

3

-

3

-

ns

Chip Selection to Power Up Time

0

-

0

-

ns

Chip Selection to Power DownTime

-

8

-

10

ns

WRITE CYCLE*

* The above parameters are also guaranteed at industrial temperature range.

Parameter

Symbol

K6R1016V1D-08

K6R1016V1D-10

Unit

Min

Max

Min

Max

Write Cycle Time

8

-

10

-

ns

Chip Select to End of Write

6

-

7

-

ns

Address Set-up Time

0

-

0

-

ns

Address Valid to End of Write

6

-

7

-

ns

Write Pulse Width(OE High)

6

-

7

-

ns

Write Pulse Width(OE Low)

8

-

10

-

ns

UB, LB Valid to End of Write

6

-

7

-

ns

Write Recovery Time

0

-

0

-

ns

Write to Output High-Z

0

4

0

5

ns

Data to Write Time Overlap

4

-

5

-

ns

Data Hold from Write Time

0

-

0

-

ns

End of Write to Output Low-Z

3

-

3

-

ns