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FS8108 データシート(PDF) 6 Page - Princeton Technology Corp

部品番号 FS8108
部品情報  Low Power Phase-Locked Loop IC
PDF  10 Pages
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メーカー  PTC [Princeton Technology Corp]
ホームページ  http://www.princeton.com.tw
Logo PTC - Princeton Technology Corp

FS8108 データシート(HTML) 6 Page - Princeton Technology Corp

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FS8108
Page 6
Jan 2003
Functional Description
Programmable Input Frequency Divider
The VCO input to the FIN pin is divided by the programmable divider and then internally
output to the phase/frequency detector (PFD) as f
V. The programmable input frequency
divider consists of a ÷ 64/65 (P/P+1) dual-modulus prescaler and a 18-bit (N) counter,
which is further comprised of a 6-bit swallow (A) counter, and a 12-bit main (B) counter.
The total divide ratio, M, is related to values for P, A, and B through the relation
with
The minimum programmable divisor for continuous counting is given by
and the valid total divide ratio range for the input
divider is
Programmable Reference Frequency Divider
The crystal oscillator output is divided by the programmable divider and then internally
output to the PFD as f
R. The programmable reference frequency divider consists of a fixed
÷ 8 (S) prescaler and a 13-bit reference (R) counter. The total divide ratio, T, is related to
values for S and R through the relation
The usable divisior range of the reference counter is
and therefore, the
valid total divide ratio range for the reference divider is
(in steps of 8.)
Serial Input Data Format
The divide ratios for the input and reference dividers are input using a 19-bit serial inter-
face consisting of separate clock (CLK), data (DATA), and latch enable (LE) lines. The
format of the serial data is shown in Fig. 1. The data on the DATA line is written to the
shift register on the rising edge of the CLK signal and is input with MSB first, and the last
bit is used as the latch select control bit. The data on the DATA line should be changed on
the falling edge of CLK, and LE should be held low while data is being written to the shift
register. Data is transferred from the shift register to one of the frequency divider latches
when LE is set high. When the latch select control bit is set low, data is loaded to the 18-
bit N-counter latch, and when the latch select control bit is set high, the 2 MSBs are
MP
1
+
() AP
B A
()
×
+
×
PB
A,
+
×
==
BA.
P
P 1
()
×
64
63
×
4032,
==
M
4032 to 262143.
=
TS R
×
8
R.
×
==
R
5 to 8191,
=
T
40 to 65528
=



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