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M95128-DW3G/PC データシート(PDF) 15 Page - STMicroelectronics

部品番号 M95128-DW3G/PC
部品情報  128 Kbit serial SPI bus EEPROM with high speed clock
PDF  44 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M95128-DW3G/PC データシート(HTML) 15 Page - STMicroelectronics

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M95128, M95128-W, M95128-R
Instructions
Doc ID 5798 Rev 13
15/44
5.2
Write Disable (WRDI)
One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction
to the device.
As shown in Figure 6, to send this instruction to the device, Chip Select (S) is driven low,
and the bits of the instruction byte are shifted in, on Serial Data Input (D).
The device then enters a wait state. It waits for a the device to be deselected, by Chip Select
(S) being driven high.
The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:
●
Power-up
●
WRDI instruction execution
●
WRSR instruction completion
●
WRITE instruction completion.
Figure 6.
Write Disable (WRDI) sequence
C
D
AI03750D
S
Q
2
1
34567
High Impedance
0
Instruction



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