STM802 datasheet(35/42 Pages) STMICROELECTRONICS

35 / 42 page

STM690, STM704, STM795, STM802, STM804, STM805, STM806

DC and AC parameters

Doc ID 10519 Rev 9

35/42

E to ECON propagation delay

VCC = VRST (max)

Reset to ECON high delay

µs

ISC

ECON short circuit current

VCC = 3.6 V, disable mode,

ECON = 0 V

0.1

0.75

2.0

Valid for ambient operating temperature: TA = –40 to 85 °C; VCC = VRST (max) to 5.5 V; and VBAT = 2.8 V (except where

noted).

VCC supply current, logic input leakage, watchdog functionality, push-button reset functionality, PFI functionality,

state of RST and RST tested at VBAT = 3.6 V, and VCC = 5.5 V. The state of RST or RST and PFO is tested at VCC = VCC

(min). Either VCC or VBAT can go to 0 V if the other is greater than 2.0 V.

VCC (min) = 1.0 V for TA = 0 °C to +85 °C.

Tested at VBAT = 3.6 V, VCC = 3.5 V and 0 V.

Guaranteed by design.

The leakage current measured on the RST pin (STM804/805) or RST pin (STM795) is tested with the reset output not

asserted (output high impedance).

Not valid for STM795/804/805 (open drain).

When VBAT > VCC > VSW, VOUT remains connected to VCC until VCC drops below VSW.

When VSW > VCC > VBAT, VOUT remains connected to VCC until VCC drops below the battery voltage (VBAT) - 75 mV.

10. The reset threshold tolerance is wider for VCC rising than for VCC falling due to the 10 mV (typ) hysteresis, which prevents

internal oscillation.

Table 7.

DC and AC characteristics (continued)

Sym

Alter-

native

Description

Test condition(1)

Min

Typ

Max

Unit

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