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M41T82 データシート(PDF) 27 Page - STMicroelectronics |
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M41T82 データシート(HTML) 27 Page - STMicroelectronics |
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27 / 61 page  M41T82-M41T83 Clock operation Doc ID 12578 Rev 12 27/61 the digital calibration circuitry uses periodic counter correction which occurs downstream of the 512 Hz divider chain and hence has no effect on the FT pin. Note: 1 The modified pulses are not observable on the frequency test (FT) output, nor will the effect of the calibration be measurable real-time, due to the periodic nature of the error compensation. 2 Positive digital calibration is performed on an eight minute cycle, therefore the value in the calibration register should not be modified more frequently than once every eight minutes for positive values of calibration. Negative digital calibration is performed on a sixteen minute cycle, therefore negative values in the calibration register should not be modified more frequently than once every sixteen minutes. |
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