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IP2005APBF データシート(PDF) 4 Page - International Rectifier

部品番号 IP2005APBF
部品情報  High Frequency Synchronous Buck Optimized LGA Power Stage
PDF  18 Pages
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メーカー  IRF [International Rectifier]
ホームページ  http://www.irf.com
Logo IRF - International Rectifier

IP2005APBF データシート(HTML) 4 Page - International Rectifier

  IP2005APBF Datasheet HTML 1Page - International Rectifier IP2005APBF Datasheet HTML 2Page - International Rectifier IP2005APBF Datasheet HTML 3Page - International Rectifier IP2005APBF Datasheet HTML 4Page - International Rectifier IP2005APBF Datasheet HTML 5Page - International Rectifier IP2005APBF Datasheet HTML 6Page - International Rectifier IP2005APBF Datasheet HTML 7Page - International Rectifier IP2005APBF Datasheet HTML 8Page - International Rectifier IP2005APBF Datasheet HTML 9Page - International Rectifier Next Button
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PD-60325
iP2005APbF
2/8/2008
www.irf.com
4
PARAMETER
MIN
TYP
MAX
UNITS
CONDITIONS
PWM INPUT
Logic Level Low Threshold (V
IL)-
-
0.8
V
Logic Level High Threshold
(V
IH)
2.0
-
-
V
Threshold Hysteresis
-
100
-
mV
Weak Pull-down impedance
-
100
-
k
Rising Propagation Delay
(T
PDH)
-60
-
ns
Falling Propagation Delay
(T
PDL)
-30
-
ns
Schmitt Trigger Input
V
DD = POR to 7.0V
(Note 4)
Electrical Specifications (continued)
These specifications apply for T
BLK = 0ºC to 125ºC and VDD = 5.0V unless otherwise specified.
Notes:
1.
Must not exceed 7.5V
2.
Block Temperature (T
BLK) is defined as any Die temperature within the package
3.
Measurement made with six 10µF (TDK C3225X5R1C106KT or equivalent) ceramic capacitors placed across VIN to
PGND pins (see Figure 8)
4.
Not associated with rise and fall times. Does not affect Power Loss



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