ADSP-BF504 datasheet(47/80 Pages) AD

47 / 80 page

Preliminary Technical Data

Rev. PrC

Page 47 of 80

January 2010

ADSP-BF504/F,ADSP-BF506F

ADC Controller Module (ACM) Timing

Table 39 and Figure 28 describe ACM operations.

Note that the ACM clock (ACLK) frequency in MHz is set by

the following equation (in which ACMCKDIV ranges from

0 to 255).

fACLK

fSCLK

2ACMCKDIV

() 2

--------------------------------------------------------

tACLK

fACLK

--------------

Table 39. ACM Timing

Parameter

DDEXT = 1.8 V

DDEXT = 2.5/3.3 V

Min

Max

Min

Max

Units

Timing Requirements

tSDR

SPORT DRxPRI/DRxSEC Setup Before ACLK

tHDR

SPORT DRxPRI/DRxSEC Hold After ACLK

Switching Characteristics

tDO

ACM Controls (ACM_A[2:0], ACM_RANGE, ACM_SGLDIFF) Delay

After Falling Edge of CLKOUT

8.4

tDACLK

ACLK Delay After Falling Edge of CLKOUT

8.4

tDCS

CS Active Edge Delay After Falling Edge of CLKOUT

5.3

tDCSACLK The Delay Between the Active Edge of CS and the First Edge of

ACLK

tACLK

Figure 28. ACM Timing

tDCSACLK

ACLK

ACM

CONTROLS

DRxPRI/

DRxSEC

CLKOUT

tDCS

tDACLK

tDO

tSDR

tHDR

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