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MSC8252 データシート(PDF) 36 Page - Freescale Semiconductor, Inc |
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MSC8252 データシート(HTML) 36 Page - Freescale Semiconductor, Inc |
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36 / 68 page ![]() MSC8252 Dual-Core Digital Signal Processor Data Sheet, Rev. 3 Electrical Characteristics Freescale Semiconductor 36 2.6 AC Timing Characteristics This section describes the AC timing characteristics for the MSC8252. 2.6.1 DDR SDRAM AC Timing Specifications This section describes the AC electrical characteristics for the DDR SDRAM interface. 2.6.1.1 DDR SDRAM Input AC Timing Specifications Table 18 provides the input AC timing specifications for the DDR SDRAM when VDDDDR (typ) = 1.8 V. Table 19 provides the input AC timing specifications for the DDR SDRAM when VDDDDR (typ) = 1.5 V. Table 20 provides the input AC timing specifications for the DDR SDRAM interface. Table 18. DDR2 SDRAM Input AC Timing Specifications for 1.8 V Interface Parameter Symbol Min Max Unit AC input low voltage VIL —MVREF – 0.20 V AC input high voltage VIH MVREF + 0.20 — V Note: At recommended operating conditions with VDDDDR of 1.8 ± 5%. Table 19. DDR3 SDRAM Input AC Timing Specifications for 1.5 V Interface Parameter Symbol Min Max Unit AC input low voltage VIL —MVREF – 0.175 V AC input high voltage VIH MVREF + 0.175 — V Note: At recommended operating conditions with VDDDDR of 1.5 ± 5%. Table 20. DDR SDRAM Input AC Timing Specifications Parameter Symbol Min Max Unit Notes Controller Skew for MDQS—MDQ/MECC/MDM • 800 MHz data rate • 667 MHz data rate tCISKEW –200 –240 200 240 ps ps 1, 2 Tolerated Skew for MDQS—MDQ/MECC/MDM • 800 MHz data rate • 667 MHz data rate tDISKEW –425 –510 425 510 ps ps 2, 3 Notes: 1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that is captured with MDQS[n]. Subtract this value from the total timing budget. 2. At recommended operating conditions with VDDDDR (1.8 V or 1.5 V) ± 5% 3. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW.This can be determined by the following equation: tDISKEW =±(T ÷ 4 – abs(tCISKEW)) where T is the clock period and abs(tCISKEW) is the absolute value of tCISKEW. |
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