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STM8L101F2P6 データシート(PDF) 23 Page - STMicroelectronics |
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STM8L101F2P6 データシート(HTML) 23 Page - STMicroelectronics |
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23 / 81 page  STM8L101xx Memory and register map Doc ID 15275 Rev 11 23/81 5 Memory and register map Figure 8. Memory map 1. Table 5 lists the boundary addresses for each memory size. The top of the stack is at the RAM end address. 2. Refer to Table 7 for an overview of hardware register mapping, to Table 6 for details on I/O port hardware registers, and to Table 8 for information on CPU/SWIM/debug module controller registers. GPIO and peripheral registers(2) 0x00 0000 Reserved Flash program memory (up to 8 Kbytes) (1) Interrupt vectors 0x00 4800 0x00 48FF RAM 0x00 05FF (1.5 Kbytes) (1) (up to 513 bytes) (1) 0x 004900 Option bytes 0x00 5000 0x00 57FF 0x00 5800 0x00 7FFF 0x00 8000 0x00 9FFF 0x00 0600 0x00 47FF 0x00 49FF 0x00 7EFF 0x00 8080 0x00 807F CPU/SWIM/Debug/ITC Registers 0x00 7F00 Reserved Reserved including Stack including Data EEPROM (up to 2 Kbytes) 0x 004925 0x 004931 0x 004924 0x 004930 Unique ID Reserved Low-density |
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