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LC72714W データシート(PDF) 6 Page - Sanyo Semicon Device |
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LC72714W データシート(HTML) 6 Page - Sanyo Semicon Device |
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6 / 29 page ![]() No. 6871-6/29 LC72714W Continued from preceding page. Pin No. Pin Function I/O Pin circuit Subcarrier input (comparator input) 56 CIN Vref – + Input Reference voltage output (Vdda/2) 52 VREF Vssa Vdda Output CCB serial interface data output 36 DO Output — — — — This pin must be left open 37 50 57 NC Analog system power supply Analog system ground Digital system power supply (+2.7 V to +3.6 V) Digital system ground 54 51 2, 15, 34 14, 35, 63 VDDA VSSA VDDD VSSD Notes: 1. This pin must be connected to VDDD or VSSD if the IC is used in serial interface mode (when SP is high). 2. A capacitor of at least 2000 pF must be inserted between VDDD and VSSD. 3. When used in the SP = high mode (as set by the serial interface), the D0 to D7 data bus lines must be connected to either VDDD or VSSD. Control Registers This IC includes both registers that can be read and registers that can be written. These registers can be accessed using either the serial interface (CCB) or the parallel interface. The SP pin switches between these interfaces. The initial values of the write registers are the data loaded into internal registers when a reset signal (RST) is received. These values are recommended values that do not need to be changed during normal operation. If the parallel interface is used, applications must hold the address fixed at 00H when reading out data to which error correction has been applied. If the CCB interface is used, the application needs only to specify the CCB address (#FB). The address 00H is an invalid address for writing. The addresses other than those specified below are control addresses particular to the IC. Applications must not specify those addresses. Address Register Function R/W Address Register Function R/W 1 BIC Number of allowable BIC errors W 1 STAT Status register R 2 SYNCB Block synchronization: error protection count W 2 BLNO Block number register R 3 SYNCF Frame synchronization: error protection count W 4 CTL1 Control register 1 W 5 CTL2 Control register 2 W 6 CRC4 Layer 4 CRC register W |
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