STK22C48

Document Number: 001-51000 Rev. *D

Page 9 of 17

AC Switching Characteristics

SRAM Read Cycle

Parameter

Description

25 ns

45 ns

Unit

Min

Max

Min

Max

Cypress

Parameter

Alt

Chip enable access time

–

25

–

45

ns

Read cycle time

25

–

45

–

ns

Address access time

–

25

–

45

ns

Output enable to data valid

–

10

–

20

ns

Output hold after address change

5

–

5

–

ns

Chip enable to output active

5

–

5

–

ns

Chip disable to output inactive

–

10

–

15

ns

Output enable to output active

0

–

0

–

ns

Output disable to output inactive

–

10

–

15

ns

Chip enable to power active

0

–

0

–

ns

Chip disable to power standby

–

25

–

45

ns

Switching Waveforms

Figure 7. SRAM Read Cycle 1: Address Controlled [6, 7]

Figure 8. SRAM Read Cycle 2: CE and OE Controlled [6]

Notes

6. WE and HSB must be High during SRAM Read cycles.

7. Device is continuously selected with CE and OE both Low.

8. Measured ±200 mV from steady state output voltage.

9. These parameters are guaranteed by design and are not tested.

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