High-Efficiency, 2A, Current-Mode

Synchronous, Step-Down Switching Regulator

______________________________________________________________________________________ 13

must always be below the minimum high-side current-

Ensure that the following relationship is satisfied:

(

)

L_PK

LOAD

L

HSCL, L_SAT

1

I

I

I

min I

I

2

=

+ ∆ <

Input Capacitor Selection

The input capacitor reduces the peak current drawn from

the input power supply and reduces switching noise in

the device. The total input capacitance must be equal to

or greater than the value given by the following equation

to keep the input ripple voltage within the specification

and minimize the high-frequency ripple current being fed

back to the input source:

LOAD

OUT

IN

SW

IN_RIPPLE

IN

I

V

C

f

V

V

=

×

× ∆

voltage across the input capacitors and is recommend-

ed to be less than 2% of the minimum input voltage,

output load. The impedance of the input capacitor at

the switching frequency should be less than that of the

input source so high-frequency switching currents do not

pass through the input source, but are instead shunted

through the input capacitor.

The input capacitor must meet the ripple current require-

ment imposed by the switching currents. The RMS input

ripple current is given by:

(

)

OUT

IN

OUT

RIPPLE

LOAD

IN

V

V

V

I

I

V





×

−





=









Output Capacitor Selection

The key selection parameters for the output capacitor

are capacitance, ESR, ESL, and voltage rating. The

parameters affect the overall stability, output ripple volt-

age, and transient response of the DC-DC converter.

The output ripple occurs due to variations in the charge

stored in the output capacitor, the voltage drop due to

the capacitor’s ESR, and the voltage drop due to the

Figure 1. Peak Current-Mode Regulator Transfer Model

L

COMPARATOR

COMP

POWER MODULATOR

OUTPUT FILTER

AND LOAD

THIS CAN BE USED TO SIMPLIFY/MODEL THE MODULATION/CONTROL/POWER

STATE CIRCUITRY SHOWN WITHIN THE BOXED AREA.

REGULATOR’S GAIN BANDWIDTH AND INCREASED PHASE

MARGIN FOR SOME LOW-DUTY CYCLE APPLICATIONS.

ERROR AMPLIFIER

FEEDBACK

DIVIDER

SLOPE

COMPENSATION

RAMP

DCR

ESR

REF

FB

R1

R2

PWM

CONTROL

LOGIC

C