Analog Integrated Circuit Device Data

4

Freescale Semiconductor

33882

PIN CONNECTIONS

4

6

9

18

21

24

27

29

9

11

13

25

28

30

32

2

21

23

25

5

8

10

12

14

IN0

IN1

IN2

IN7

IN3

IN4

IN5

IN6

Input 0–Input7

These are parallel control input pins. These pins have internal 25

μA active

pull-downs.

5

7

10

17

20

23

26

30

10

12

14

24

27

29

31

3

22

24

26

4

7

9

11

15

OUT0

OUT1

OUT2

OUT7

OUT3

OUT4

OUT5

OUT6

Output 0–Output7

Each pin is one channel's drain, sinking current for the respective load.

8, 11, 22,

25

2,31

NC

No Connect

Not connected.

12

15

27

SI

Serial Input

The Serial Input pin is connected to the SPI Serial Data Output pin of the

control IC from where it receives output command data. This input has an

internal active 25

μA pull-down and requires CMOS logic levels.

13

16

28

SCLK

Serial Clock

The SCLK pin of the control IC is a bit (shift) clock for the SPI port. It

transitions one time per bit transferred when in operation. It is idle between

command transfers. It is 50% duty cycle, and has CMOS levels.

14

17

29

CS

Chip Select

This pin is connected to a chip select output of the control IC. This input has

an internal active 25

μA pull-up and requires CMOS logic levels.

15

18

30

SO

Serial Output

This pin is connected to the SPI Serial Data Input pin of the control IC or to

the SI pin of the next device in a daisy chain. This output will remain tri-

low. The output signal generated will have CMOS logic levels and the output

data will transition on the falling edges of SCLK. The serial output data

provides fault information for each output and is returned MSB first when the

device is addressed.

16

23

3

VDD

Logic Supply Voltage This pin is connected to the 5.0 V power supply of the system. A decoupling

capacitor is required from VDD to ground.

Heat

Sink

(exposed

pad)(1)

4,5,19-

22

1,16,17,

32

GND

Ground

Ground continuity is required for the outputs to turn on. The heatsink must

be electrically connected to GND.

Notes

1.

The exposed pad on this package provides the circuit ground connection for the IC.

Table 1. HSOP Pin Function Description (continued)

30 Pin

HSOP

32 Pin

QFN

32 Pin

SOIC

Pin Name

Formal Name

Definition