900844 datasheet(76/118 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

900844

FUNCTIONAL DEVICE OPERATION

POWER SUPPLIES

Figure 41. VCCPDDR Detailed Internal Block Diagram

Main Features

• Uses V15 as the main power supply

•60 mA maximum continuous output current

• Optimized for a 1.0 µF external filter capacitor with a maximum of 10 m

Ω ESR

• Uses an internal pass FET

• The output for each LDO is monitored for over-current conditions and under-voltage events

VAON

VAON is a low drop-out (LDO) fully integrated regulator with a P-CH Pass FET. It is high performance, low noise, and high

PSRR, with a low quiescent current and fast transient response. VAON is actively discharged during shutdown.

VAON shares an input voltage pin (PVIN1P5) and a reference ground pin (GND1P5) with the VCCPAOAC, VCCPDDR, VMM,

and VCCP regulators, yet each has independent control. PVIN1P5 is supplied from the V15 voltage.

Table 38. VCCPDDR Control Register Structure and Bits Description

Name

Bits

Description

VCCPDDRCNT (ADDR 0x3E - R/W - Default value: 0x3C)

CTLVCCPDDR

2:0

VCCPDDR State Control

x0 = Reserved

x1 = Reserved

x2 = Reserved

x3 = Reserved

x4 = OFF

x5 = Low Power

x6 = Active

x7 = Active

AOACCTLVCCPDDR

5:3

VCCPDDR State Control during AOAC Exit (when the Exit pin is EXITSTBY pin is asserted). These bits will be

initialized by the system SPI controller after power up.

X0 = Do not copy

x1 = Do not copy

x2 = Do not copy

x3 = Do not copy

x4 = OFF

x5 = Low Power

x6 = Active

x7 = Active

Reserved

7:6

Reserved

Controller

VOCCPDDR

PVIN 1P5

(Shared with VCCPAOAC, VAON ,

VMM, and VCCP)

VOUTCCPDDR

Output Monitor

IOCCPDDR

SPI

Interface

COCCPDDR

VOCCPDDR

CTLVCCPDDR

AOACCTLVCCPDDR

VCCPDDRFAULT

VREF

Discharge

FBCCPDDR

GND1P5

(Shared with VCCPAOAC, VAON ,

VMM, and VCCP)

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