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PTN3700 データシート(PDF) 10 Page - NXP Semiconductors

部品番号 PTN3700
部品情報  1.8 V simple mobile interface link bridge IC Very low power profile
PDF  43 Pages
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メーカー  NXP [NXP Semiconductors]
ホームページ  http://www.nxp.com
Logo NXP - NXP Semiconductors

PTN3700 データシート(HTML) 10 Page - NXP Semiconductors

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PTN3700
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 8 June 2011
10 of 43
NXP Semiconductors
PTN3700
1.8 V simple mobile interface link bridge IC
7.2 Link programmability
The number of high-speed serial channels used is programmed by CMOS input pins
LS[1:0]. For a given link consisting of a transmitter and receiver pair of PTN3700’s, the
number of channels used must be programmed identically or the link will malfunction. The
PTN3700, once programmed, will assume the corresponding serialization ratio as shown
in Table 5. When pins LS[1:0] are both HIGH, the PTN3700 is put in a test mode which is
used for production testing purposes only and should not be used in application.
The 1-lane mode is typically meant for smaller video display formats (e.g., QVGA to
HVGA), while the 2-lane mode is typically used for display formats like HVGA and VGA.
The 3-lane mode supports larger display formats such as VGA or XGA. Please see
Section 12.1 for more information.
[1]
Mode 11 is used for test purposes only.
7.3 Versatile signal mirroring programmability
In order to provide flexibility for different signal order and flow requirements in different
applications, the PTN3700 can be programmed to mirror its signal order for the parallel
and serial I/Os independently using the PSEL[1:0] inputs. The signal order also changes
as a function of the TX/RX input by mirroring signals in such a way that the Transmitter
and Receiver in a given link can be connected without signal crossings by simply
opposing the two instances of PTN3700 and rotating one of them by 180 degrees. The
truth table for the versatile signal mirroring scheme is shown in Table 6 and Table 7. The
individual ball mappings are given in Figure 4 through Figure 11.
Table 5.
Link programmability
LS1
LS0
Mode
Number of
high-speed
serial channels
Supported PCLK
frequency range (MHz)
Guaranteed data
bandwidth per
channel (Mbit/s)
Guaranteed
aggregate link
bandwidth (Mbit/s)
L
L
00
1
4.0 to 21.6
120 to 650
650
L
H
01
2
8.0 to 43.3
120 to 650
1300
H
L
10
3
20.0 to 65.0
200 to 650
1950
H
H
11
reserved[1]
reserved
reserved
reserved



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