ADP5033ACBZ-1-R7 datasheet(23/28 Pages) AD

部品番号	ADP5033ACBZ-1-R7

部品情報	Dual 3 MHz, 800 mA Buck Regulators with Two 300 mA LDOs

PDF	28 Pages

Scroll/Zoom	100%

メーカー	AD [Analog Devices]

ホームページ	http://www.analog.com

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23 / 28 page

ADP5033

Rev. 0 | Page 23 of 28

PCB LAYOUT GUIDELINES

Poor layout can affect ADP5033 performance, causing electro-

magnetic interference (EMI) and electromagnetic compatibility

(EMC) problems, ground bounce, and voltage losses. Poor

layout can also affect regulation and stability. A good layout is

implemented using the following guidelines:

•

Place the inductor, input capacitor, and output capacitor

close to the IC using short tracks. These components carry

high switching frequencies, and large tracks act as antennas.

•

Route the output voltage path away from the inductor and

SW node to minimize noise and magnetic interference.

•

Maximize the size of ground metal on the component side

to help with thermal dissipation.

•

Use a ground plane with several vias connecting to the

component side ground to further reduce noise interfer-

ence on sensitive circuit nodes.

•

Connect VIN1 and VIN2 together close to the IC using

short tracks.

ADP5033ACBZ-1-R7 データシート(PDF) 23 Page - Analog Devices