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CY2DP1502ZXIT データシート(PDF) 4 Page - Cypress Semiconductor

部品番号 CY2DP1502ZXIT
部品情報  1:2 LVPECL Fanout Buffer 20-ps maximum output-to-output skew
PDF  13 Pages
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メーカー  CYPRESS [Cypress Semiconductor]
ホームページ  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY2DP1502ZXIT データシート(HTML) 4 Page - Cypress Semiconductor

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CY2DP1502
Document Number: 001-56308 Rev. *G
Page 4 of 13
DC Electrical Specifications
(VDD = 3.3 V ± 5% or 2.5 V ± 5%; TA = 0 °C to 70 °C (Commercial) or –40 °C to 85 °C (Industrial))
Parameter
Description
Condition
Min
Max
Unit
IDD
Operating supply current
All LVPECL outputs floating (internal IDD)–
45
mA
VIH
Input high voltage, LVPECL inputs
IN and IN#
–VDD + 0.3
V
VIL
Input low voltage, LVPECL inputs
IN and IN#
–0.3
V
VID
[3]
Input differential amplitude
See Figure 2 on page 6
0.4
1.0
V
VICM
Input common mode voltage
See Figure 2 on page 6
0.5
VDD – 0.2
V
IIH
Input high current, LVPECL inputs
IN and IN#
Input = VDD
[4]
150
A
IIL
Input low current, LVPECL inputs
IN and IN#
Input = VSS
[4]
–150
A
VOH
LVPECL output high voltage
Terminated with 50
 to V
DD – 2.0
[5]
VDD – 1.20 VDD – 0.70
V
VOL
LVPECL output low voltage
Terminated with 50
 to V
DD – 2.0
[5]
VDD – 2.0 VDD – 1.63
V
CIN
Input capacitance
Measured at 10 MHz; per pin
3
pF
Notes
3. VID minimum of 400 mV is required to meet all output AC Electrical Specifications. The device is functional with VID minimum of greater than 200 mV.
4. Positive current flows into the input pin, negative current flows out of the input pin.
5. Refer to Figure 3 on page 6.



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