PCF8593P datasheet(21/35 Pages) NXP

21 / 35 page

PCF8593

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 04 — 6 October 2010

21 of 35

NXP Semiconductors

PCF8593

Low power clock and calendar

10.2 Dynamic characteristics

[1]

Event counter mode only.

[2]

All timing values are valid within the operating supply voltage, ambient temperature range, reference to VIL and VIH and with an input

voltage swing of VSS to VDD.

Table 8.

Dynamic characteristics

VDD = 2.5 V to 6.0 V; VSS = 0 V; Tamb = −40 °C to +85 °C unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Oscillator

COSCO

capacitance on pin OSCO

Δf

osc/fosc

relative oscillator frequency

variation

for

ΔV

DD = 100 mV; Tamb =25 °C;

VDD = 1.5 V

-0.2

-ppm

fclk(ext)

external clock frequency

[1]

--1

MHz

Quartz crystal parameters (f = 32.768 kHz)

series resistance

parallel load capacitance

Ctrim

trimmer capacitance

I2C-bus timing (see Figure 21)[2]

fSCL

SCL clock frequency

100

kHz

tSP

pulse width of spikes that

must be suppressed by the

input filter

--100

tBUF

bus free time between a

STOP and START condition

4.7

μs

tSU;STA

set-up time for a repeated

START condition

4.7

μs

tHD;STA

hold time (repeated) START

condition

4.0

μs

tLOW

LOW period of the SCL clock

4.7

μs

tHIGH

HIGH period of the SCL clock

4.0

μs

rise time of both SDA and

SCL signals

--1.0

μs

fall time of both SDA and SCL

signals

--0.3

μs

tSU;DAT

data set-up time

250

tHD;DAT

data hold time

tVD;DAT

data valid time

3.4

μs

tSU;STO

set-up time for STOP

condition

4.0

μs

PCF8593P データシート(PDF) 21 Page - NXP Semiconductors

PCF8593P データシート(HTML) 21 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35

データシートダウンロード