PCF8591_03 datasheet(9/28 Pages) PHILIPS

9 / 28 page

2003 Jan 27

Philips Semiconductors

Product speciﬁcation

8-bit A/D and D/A converter

PCF8591

7.4

A/D conversion

The A/D converter makes use of the successive

approximation conversion technique. The on-chip D/A

converter and a high-gain comparator are used

temporarily during an A/D conversion cycle.

An A/D conversion cycle is always started after sending a

valid read mode address to a PCF8591 device. The A/D

conversion cycle is triggered at the trailing edge of the

acknowledge clock pulse and is executed while

transmitting the result of the previous conversion (see

Fig.9).

Once a conversion cycle is triggered an input voltage

sample of the selected channel is stored on the chip and is

converted to the corresponding 8-bit binary code. Samples

picked up from differential inputs are converted to an 8-bit

twos complement code (see Figs 10 and 11).

The conversion result is stored in the ADC data register

and awaits transmission. If the auto-increment flag is set

the next channel is selected.

The first byte transmitted in a read cycle contains the

conversion result code of the previous read cycle. After a

Power-on reset condition the first byte read is a

hexadecimal 80. The protocol of an I2C-bus read cycle is

shown in Chapter 8, Figs 16 and 17.

The maximum A/D conversion rate is given by the actual

speed of the I2C-bus.

handbook, full pagewidth

ADDRESS

DATA BYTE 1

DATA BYTE 2

DATA BYTE 0

PROTOCOL

SCL

SDA

conversion of byte 2

conversion of byte 3

conversion of byte 1

transmission

of previously

converted byte

sampling byte 2

sampling byte 3

sampling byte 1

transmission

of byte 1

transmission

of byte 2

MBL829

Fig.9 A/D conversion sequence.

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