TMS570LS3137 datasheet(132/159 Pages) TI

132 / 159 page

VCCIO

0.6*VCCIO

0.4*VCCIO

Input

tpw

0.6*VCCIO

0.4*VCCIO

TMS570LS3137

SPNS162.

– SEPTEMBER 2011

www.ti.com

5.5

FlexRay Interface

The FlexRay module performs communication according to the FlexRay protocol specification v2.1. The

sample clock bitrate can be programmed to values up to 10 MBit per second. Additional bus driver (BD)

hardware is required for connection to the physical layer.

For communication on a FlexRay network, individual message buffers with up to 254 data bytes are

configurable. The message storage consists of a single-ported message RAM that holds up to 128

message buffers. All functions concerning the handling of messages are implemented in the message

handler. Those functions are the acceptance filtering, the transfer of messages between the two FlexRay

Channel Protocol Controllers and the message RAM, maintaining the transmission schedule as well as

providing message status information.

The register set of the FlexRay module can be accessed directly by the CPU via the VBUS interface.

These registers are used to control, configure and monitor the FlexRay channel protocol controllers,

message handler, global time unit, system universal control, frame/symbol processing, network

management, interrupt control, and to access the message RAM via the input / output buffer.

5.5.1

Features

The FlexRay module has the following features:

•

Conformance with FlexRay protocol specification v2.1

•

Data rates of up to 10 Mbit/s on each channel

•

Up to 128 message buffers

•

8 Kbyte of message RAM for storage of e.g. 128 message buffers with max. 48 byte data section or up

to 30 message buffers with 254 byte data section

•

Configuration of message buffers with different payload lengths

•

One configurable receive FIFO

•

Each message buffer can be configured as receive buffer, as transmit buffer or as part of the receive

FIFO

•

CPU access to message buffers via input and output buffer

•

FlexRay Transfer Unit (FTU) for automatic data transfer between data memory and message buffers

without CPU interaction

•

Filtering for slot counter, cycle counter, and channel ID

•

Maskable module interrupts

•

Supports Network Management

5.5.2

Electrical and Timing Specifications

Table 5-15. Timing Requirements for FlexRay Inputs(1)

Parameter

MIN

MAX

UNIT

tpw

Input minimum pulse width to meet the FlexRay sampling

tc(AVCLK2) + 2.5

(2)

requirement

(1)

tc(AVCLK2) = sample clock cycle time for FlexRay = 1 / f(AVCLK2)

(2)

tRxAsymDelay parameter

Figure 5-8. FlexRay Inputs

132

Peripheral Information and Electrical Specifications

Submit Documentation Feedback

focus.ti.com: TMS570LS3137

TMS570LS3137 データシート(PDF) 132 Page - Texas Instruments

TMS570LS3137 データシート(HTML) 132 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

データシートダウンロード