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TMS570LS3137 データシート(PDF) 138 Page - Texas Instruments |
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TMS570LS3137 データシート(HTML) 138 Page - Texas Instruments |
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138 / 159 page  SDA SCL t w(SDAH) t w(SCLL) t w(SCLH) t w(SP) t h(SCLL-SDAL) t h(SDA-SCLL) t h(SCLL-SDAL) t su(SCLH-SDAL) t f(SCL) t c(SCL) t r(SCL) t su(SCLH-SDAH) Stop Start Repeated Start Stop t su(SDA-SCLH) TMS570LS3137 SPNS162. – SEPTEMBER 2011 www.ti.com 5.9.2 I2C I/O Timing Specifications Table 5-18. I2C Signals (SDA and SCL) Switching Characteristics(1) Parameter Standard Mode Fast Mode Unit MIN MAX MIN MAX tc(I2CCLK) Cycle time, Internal Module clock for I2C, 75.2 149 75.2 149 ns prescaled from VCLK tc(SCL) Cycle time, SCL 10 2.5 ms tsu(SCLH-SDAL) Setup time, SCL high before SDA low (for a 4.7 0.6 ms repeated START condition) th(SCLL-SDAL) Hold time, SCL low after SDA low (for a repeated 4 0.6 ms START condition) tw(SCLL) Pulse duration, SCL low 4.7 1.3 ms tw(SCLH) Pulse duration, SCL high 4 0.6 ms tsu(SDA-SCLH) Setup time, SDA valid before SCL high 250 100 ns th(SDA-SCLL) Hold time, SDA valid after SCL low (for I2C bus 0 3.45(2) 0 0.9 ms devices) tw(SDAH) Pulse duration, SDA high between STOP and 4.7 1.3 ms START conditions tsu(SCLH-SDAH) Setup time, SCL high before SDA high (for STOP 4.0 0.6 ms condition) tw(SP) Pulse duration, spike (must be suppressed) 0 50 ns Cb (3) Capacitive load for each bus line 400 400 pF (1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down. (2) The maximum th(SDA-SCLL) for I2C bus devices has only to be met if the device does not stretch the low period (tw(SCLL)) of the SCL signal. (3) Cb = The total capacitance of one bus line in pF. Figure 5-9. I2C Timings 138 Peripheral Information and Electrical Specifications Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback focus.ti.com: TMS570LS3137 |
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