L3G4200D datasheet(20/42 Pages) STMICROELECTRONICS

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Application hints

L3G4200D

20/42

Doc ID 17116 Rev 3

Application hints

Figure 12.

L3G4200D electrical connections and external component values

Power supply decoupling capacitors (100 nF ceramic or polyester +10 µF) should be placed

as near as possible to the device (common design practice).

If Vdd and Vdd_IO are not connected together, power supply decoupling capacitors

(100 nF and 10 µF between Vdd and common ground, 100 nF between Vdd_IO and

common ground) should be placed as near as possible to the device (common design

practice).

The L3G4200D IC includes a PLL (phase locked loop) circuit to synchronize driving and

sensing interfaces. Capacitors and resistors must be added at the PLLFILT pin (as shown in

Figure 12) to implement a second-order low-pass filter. Table 10 summarizes the PLL low-

pass filter component values.

Table 10.

PLL low-pass filter component values

Component

Value

10 nF ± 10 %

470 nF ± 10 %

10 k

Ω ± 10 %

100 nF

10kOhm

470nF

Vdd

GND

10 µF

SCL/SPC

SDO/SA0

SDA_SDI_SDO

10nF

Vdd_IO

TOP

VIEW

INT

(TOP VIEW)

DIRECTIONS OF THE

DETECTABLE

ANGULAR RATES

+Ω

Vdd I2C bus

Rpu = 10kOhm

Rpu

SCL/SPC

SDA_SDI_SDO

Pull-up to be added when I2C interface is used

AM07949V1

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