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ICS5342 データシート(PDF) 5 Page - Integrated Device Technology |
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ICS5342 データシート(HTML) 5 Page - Integrated Device Technology |
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5 / 35 page  ICS5342 GENDAC 5 1 1 0 Command This 8-bit register selects color mode, for instance 8-bit Pseudo Color, Hi-Color, True Color, or XGA, and DAC power down. The registers are reset to pseudo color mode on power up. 1 0 1 PLL Parameter There are 16 PLL parameter registers accessible as indexed by Read/Write registers. Parameter registers 0F and 0D-00 are two bytes long and 0E is one byte long. Register 0E is a control reg- ister. The bits of this register include clock select and enable functions, the rest contain PLL frequency parameters. After writ- ing the start index address in the PLL address register, these reg- isters can be accessed in successive two (or one) bytes. The address register auto increments after one (0E) or two bytes to access the entire register Internal Registers RS2 RS1 RS0 Register Name Description (all registers can be written to and read from) ICS5342 16-Bit Integrated Clock-LUT-DAC TSD IDT™ / ICS™ 16-Bit Integrated Clock-LUT-DAC ICS5342 5 |
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