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Phone: 978-250-3343

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4

4 - 2

HMC905LP3E

v00.0310

6 GHz LOW NOISE PROGRAMMABLE

DIVIDER (N = 1 to 4)

Input Sensitivity Window

Phase Noise for 3 Cascaded

HMC905LP3E from 6 GHz VCO

Residual Phase Noise

Parameter

conditions

Min.

typ.

Max.

units

isolation se input to se output

en bit oFF

-80

-30

dBc

Duty cycle for Differential Mode

50

%

Logic Inputs

viH input High voltage

1.5

3.3

v

viL input Low voltage

0

0.8

v

Power Supplies

vcc

Analog supply

(Low noise LDo for good phase noise -

HMc860LP3e)

3.15

3.3

3.45

v

current consumption

82

100

125

mA

sleep current

en = 0v

1

µA

[1] the bias bits combination BiAs1 BiAs0 = 1 1 is not recommended

[2] Fin = 6 GHz, Pin = 6 dBm, ctrL = 1, BiAs1 BiAs0 = 01

-20

-15

-10

-5

0

5

10

0

1

2

3

4

5

6

7

BIAS1BIAS0=01

BIAS1BIAS0=00

BIAS1BIAS0=01

Operating Window

INPUT FREQUENCY (GHz)

Recommended

Operating Window

-170

-150

-130

-110

-90

-70

-50

-30

-10

10

100

1000

10

4

10

5

10

6

10

7

VCO IN

Div By 4

Div By 16

Div By 64

OFFSET FREQUENCY (Hz)

-170

-160

-150

-140

-130

-120

-110

10

100

1000

10

4

10

5

10

6

10

7

10

8

Div By 1

Div By 2

Div By 3

Div By 4

OFFSET FREQUENCY (Hz)

Output Phase Noise vs. Input Power

Divide-by-4

-170

-160

-150

-140

-130

-120

-110

-100

-90

1000

10

4

10

5

10

6

10

7

Source IN

Div By 4 0dBm

Div By 4 3dBm

Div By 4 6dBm

Div By 4 9dBm

OFFSET FREQUENCY (Hz)

All data plots taken on Evaluation Board (schematic on page 10) single-ended with the unused

output port 50 ohms terminated, Vcc = +3.3V, Ta=+25 °C, except stated otherwise