PIC24F16KA102_11 datasheet(26/278 Pages) MICROCHIP

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PIC24F16KA102 FAMILY

DS39927C-page 26

 2008-2011 Microchip Technology Inc.

3.2

CPU Control Registers

SR: ALU STATUS REGISTER

U-0

R/W-0, HSC

—

—DC

bit 15

bit 8

R/W-0, HSC(1) R/W-0, HSC(1) R/W-0, HSC(1)

R-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC

IPL2(2)

IPL1(2)

IPL0(2)

bit 7

bit 0

Legend:

HSC = Hardware Settable/Clearable bit

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15-9

Unimplemented:

Read as ‘0’

bit 8

DC:

ALU Half Carry/Borrow bit

= A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)

of the result occurred

= No carry-out from the 4th or 8th low-order bit of the result has occurred

bit 7-5

IPL<2:0>:

CPU Interrupt Priority Level Status bits(1,2)

111

= CPU interrupt priority level is 7 (15); user interrupts disabled

110

= CPU interrupt priority level is 6 (14)

101

= CPU Interrupt priority level is 5 (13)

100

= CPU interrupt priority level is 4 (12)

011

= CPU interrupt priority level is 3 (11)

010

= CPU interrupt priority level is 2 (10)

001

= CPU interrupt priority level is 1 (9)

000

= CPU interrupt priority level is 0 (8)

bit 4

RA: REPEAT

Loop Active bit

= REPEAT loop in progress

= REPEAT loop not in progress

bit 3

ALU Negative bit

= Result was negative

= Result was non-negative (zero or positive)

bit 2

OV:

ALU Overflow bit

= Overflow occurred for signed (2’s complement) arithmetic in this arithmetic operation

= No overflow has occurred

bit 1

ALU Zero bit

= An operation, which effects the Z bit, has set it at some time in the past

= The most recent operation, which effects the Z bit, has cleared it (i.e., a non-zero result)

bit 0

ALU Carry/Borrow bit

= A carry-out from the Most Significant bit (MSb) of the result occurred

= No carry-out from the Most Significant bit (MSb) of the result occurred

Note 1:

The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1.

The IPL Status bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU Interrupt Priority

Level (IPL). The value in parentheses indicates the IPL when IPL3 = 1.

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