TSL2571 datasheet(5/24 Pages) TAOS

5 / 24 page

TSL2571

LIGHT-TO-DIGITAL CONVERTER

TAOS117A − FEBRUARY 2011

The LUMENOLOGY

r Company

E 2011, TAOS Inc.

www.taosinc.com

Wait Characteristics, VDD = 3 V, TA = 255C, WEN = 1 (unless otherwise noted)

PARAMETER

TEST CONDITIONS

CHANNEL

MIN

TYP

MAX

UNIT

Wait step size

WTIME = 0xFF

2.58

2.72

2.9

Wait number of integration steps

256

steps

AC Electrical Characteristics, VDD = 3 V, TA = 255C (unless otherwise noted)

PARAMETER†

TEST CONDITIONS

MIN

TYP

MAX

UNIT

f(SCL)

Clock frequency (I2C only)

400

kHz

t(BUF)

Bus free time between start and stop condition

1.3

μs

t(HDSTA)

Hold time after (repeated) start condition. After

this period, the first clock is generated.

0.6

μs

t(SUSTA)

Repeated start condition setup time

0.6

μs

t(SUSTO)

Stop condition setup time

0.6

μs

t(HDDAT)

Data hold time

μs

t(SUDAT)

Data setup time

100

t(LOW)

SCL clock low period

1.3

μs

t(HIGH)

SCL clock high period

0.6

μs

Clock/data fall time

300

Clock/data rise time

300

Input pin capacitance

† Specified by design and characterization; not production tested.

PARAMETER MEASUREMENT INFORMATION

SDA

SCL

Stop

Start

SCLACK

t(LOWMEXT)

t(LOWSEXT)

SCLACK

t(LOWMEXT)

Start

Condition

Stop

Condition

SDA

t(SUSTO)

t(SUDAT)

t(HDDAT)

t(BUF)

VIH

VIL

SCL

t(SUSTA)

t(HIGH)

t(F)

t(R)

t(HDSTA)

t(LOW)

VIH

VIL

Figure 1. Timing Diagrams

TSL2571 データシート(PDF) 5 Page - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS

TSL2571 データシート(HTML) 5 Page - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

データシートダウンロード