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SSM2518CPZ-R7 データシート(PDF) 15 Page - Analog Devices

部品番号 SSM2518CPZ-R7
部品情報  Digital Input Stereo, 2 W, Class-D
PDF  48 Pages
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
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SSM2518CPZ-R7 データシート(HTML) 15 Page - Analog Devices

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Data Sheet
SSM2518
Rev. A | Page 15 of 48
MCLK pin to serve as the internal bit clock as well. In this case,
tie the BCLK pin to ground.
Once the SSM2518 has entered its power-down state, it is
possible to gate the clocks to conserve system power. However, a
valid master clock must be present for the audio amplifier to
operate. It is best to use a low jitter clock (less than 1 ns peak-
to-peak) to ensure the specified audio performance.



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