8

Rev: A Date:1/27/04

SP504 Multi–Mode Serial Transceivers

© Copyright 2004 Sipex Corporation

Figure 3a. Driver/Receiver Timing Test Circuit

Figure 3b. Timing Test Ckt. (V.35 mode only for SP504)

15pF

RO

A

B

A

B

DI

Figure 4. Driver Timing Test Load #2 Circuit

Figure 1. Driver DC Test Load Circuit

Figure 2. Receiver Timing Test Load Circuit

15pF

RO

A

B

A

B

DI

A

B

R

R

500Ω

Output

Under

Test

1KΩ

1KΩ

Receiver

Output

Test Point

Note : Figures 3a and 3b shown above are used for evaluating maximum transmission rate. For 10Mbps transmission rate, an input signal of 5MHz is applied

to the driver input. In order for a valid transmission rate, the driver output must adhere to the output electrical specifications (V

acceptable duty cycle for the protocol tested. The receiver outputs are checked for proper TTL/CMOS V

duty cycle.