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240800 データシート(PDF) 29 Page - Intel Corporation

部品番号 240800
部品情報  8XC196NU COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
PDF  43 Pages
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メーカー  INTEL [Intel Corporation]
ホームページ  http://www.intel.com
Logo INTEL - Intel Corporation

240800 データシート(HTML) 29 Page - Intel Corporation

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PRELIMINARY
25
8XC196NU COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
6.2.3
AC CHARACTERISTICS — MULTIPLEXED BUS MODE
Test Conditions: Capacitive load on all pins = 50 pF, Rise and Fall Times = 3 ns.
Table 12. AC Characteristics the 8XC196NU Will Meet, Multiplexed Bus Mode
Symbol
Parameter
Min
Max
Units
F
XTAL
1
Frequency on XTAL1, PLL in 1x mode
16
50 (1)
MHz
Frequency on XTAL1, PLL in 2x mode
8 (2)
25
MHz
Frequency on XTAL1, PLL in 4x mode
8 (2)
12.5
MHz
f
Operating frequency, f = F
XTAL1; PLL in 1x mode
16
50
MHz
Operating frequency, f = 2F
XTAL1; PLL in 2x mode
Operating frequency, f = 4F
XTAL
1; PLL in 4x mode
t
Period, t = 1/f
20
62.5
ns
T
XHCH
XTAL1 Rising Edge to CLKOUT High or Low
3
50
ns
T
CLCL
CLKOUT Cycle Time
2t
ns
T
CHCL
CLKOUT High Period
t – 10
t + 15
ns
T
AVWL
Address Valid to WR# Falling Edge
2t – 25
ns
T
CLLH
CLKOUT Falling Edge to ALE Rising Edge
– 10
10
ns
T
LLCH
ALE Falling Edge to CLKOUT Rising Edge
– 15
15
ns
T
LHLH
ALE Cycle Time
4t
ns (3)
T
LHLL
ALE High Period
t – 10
t + 10
ns
T
AVLL
Address Valid to ALE Falling Edge
t – 14
ns
T
LLAX
Address Hold after ALE Falling Edge
t – 10
ns
T
LLRL
ALE Falling Edge to RD# Falling Edge
t – 15
ns
T
RLCL
RD# Low to CLKOUT Falling Edge
– 10
20
ns
T
RLRH
RD# Low Period
t – 10
ns (3)
T
RHLH
RD# Rising Edge to ALE Rising Edge
t – 5
t + 15
ns (4)
T
RLAZ
RD# Low to Address Float
5
ns
T
LLWL
ALE Falling Edge to WR# Falling Edge
t – 11
ns
T
QVWH
Data Stable to WR# Rising Edge
t – 14
ns (3)
T
CHWH
CLKOUT High to WR# Rising Edge
– 15
5
ns
NOTES:
1.
25 MHz is the maximum input frequency when using an external crystal oscillator; however, 50 MHz
can be applied with an external clock source.
2.
When the phase-locked loop (PLL) circuitry is enabled, the minimum input frequency on XTAL1 is 8
MHz. The PLL cannot be run at frequencies lower than 16 MHz.
3.
If wait states are used, add 2t
× n, where n = number of wait states.
4.
Assuming back-to-back bus cycles.
5.
8-bit bus only.



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