CSD87331Q3D

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SLPS283A

– SEPTEMBER 2011 – REVISED JANUARY 2012

RECOMMENDED PCB DESIGN OVERVIEW

There are two key system-level parameters that can be addressed with a proper PCB design: Electrical and

Thermal performance. Properly optimizing the PCB layout will yield maximum performance in both areas. A brief

description on how to address each parameter is provided.

Electrical Performance

The Power Block has the ability to switch voltages at rates greater than 10kV/

µs. Special care must be then

taken with the PCB layout design and placement of the input capacitors, Driver IC, and output inductor.

•

The placement of the input capacitors relative to the Power Block

’s VIN and PGND pins should have the

highest priority during the component placement routine. It is critical to minimize these node lengths. As such,

ceramic input capacitors need to be placed as close as possible to the VIN and PGND pins (see Figure 34).

The example in Figure 34 uses 6

× 10-µF ceramic capacitors (TDK Part # C3216X5R1C106KT or equivalent).

Notice there are ceramic capacitors on both sides of the board with an appropriate amount of vias

interconnecting both layers. In terms of priority of placement next to the Power Block, C5, C7, C19, and C8

should follow in order.

•

should be connected to the Phase pin of the IC (sometimes called LX, LL, SW, PH, etc.). The bootstrap

capacitor for the Driver IC will also connect to this pin.

•

The switching node of the output inductor should be placed relatively close to the Power Block VSW pins.

Minimizing the node length between these two components will reduce the PCB conduction losses and

reaches undesirable levels, the use of a Boost Resistor or RC snubber can be an effective way to easily

reduce the peak ring level. The recommended Boost Resistor value will range between 1.0 Ohms to 4.7

Ohms depending on the output characteristics of Driver IC used in conjunction with the Power Block. The RC

snubber values can range from 0.5 Ohms to 2.2 Ohms for the R and 330pF to 2200pF for the C. Please refer

to TI App Note SLUP100 for more details on how to properly tune the RC snubber values. The RC snubber

should be placed as close as possible to the Vsw node and PGND see Figure 34(1)

(1)

(1) Keong W. Kam, David Pommerenke,

“EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University

of Missouri

– Rolla

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© 2011–2012, Texas Instruments Incorporated

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