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THS8083CPZP データシート(PDF) 44 Page - Texas Instruments |
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THS8083CPZP データシート(HTML) 44 Page - Texas Instruments |
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44 / 61 page  4–4 4.4 Timing Diagram – 48-Bit Parallel Mode This mode allows a double-pixel width output interface with no time offset between buses A and B. The DATACLK1 output is at half of the sampling clock frequency. Last Samples From Previous Line DATACLK CH1_OUTA[7..0] CH2_OUTA[7..0] CH2_OUTB[7..0] CH1_OUTB[7..0] CH3_OUTA[7..0] CH3_OUTB[7..0] HS 01 05 DHS tdlh(OE) tdhl(OE) tsu(DHS) th(DHS) tsu(OUT) (DHS_POL = 0 Assumed-Inverted Polarity Otherwise) OE <DHS_MODE> = 1 –> Width Equal to Width of HS Input <DHS_MODE> = 0 –> DHS Width is 1 ADCCLK2 Period 7 ADCCLK2 Cycles Latency pix 01 pix 02 ADCCLK1 Last Samples From Previous Line 03 th(OUT) 04 02 01 05 Last Samples From Previous Line 03 Last Samples From Previous Line 04 02 01 05 Last Samples From Previous Line 03 Last Samples From Previous Line 04 02 7 ADCCLK2 Cycles Latency |
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