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TNETA1575 データシート(PDF) 32 Page - Texas Instruments

部品番号 TNETA1575
部品情報  ATM SEGMENTATION AND REASSEMBLY DEVICE WITH PCI-HOST AND COPROCESSOR INTERFACES
PDF  45 Pages
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メーカー  TI1 [Texas Instruments]
ホームページ  http://www.ti.com
Logo TI1 - Texas Instruments

TNETA1575 データシート(HTML) 32 Page - Texas Instruments

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TNETA1575
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH PCI-HOST AND COPROCESSOR INTERFACES
SDNS040C – MAY 1996 – REVISED JUNE 1998
32
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
timing requirements (see Figure 14)
control-memory interface – read operation
NO.
MIN
MAX
UNIT
1
tsu(CMDATA)
Setup time, CMDATA31–CMDATA0 valid before PCLK
↑
3
ns
2
th(CMDATA)
Hold time, CMDATA31–CMDATA0 valid after PCLK
↑
3
ns
operating characteristics (see Figure 14)
control-memory interface read operation
NO.
PARAMETER
MIN
MAX
UNIT
3
td(CMAD)
Delay time, from PCLK
↑ to CMAD15–CMAD0 valid
5
15
ns
4
td(CMOE)
Delay time, from PCLK
↑ to CMOE↓
8
15
ns
CMAD15-
CMAD0
(output)
CMOE
(output)
CMWE
(output)
Valid
CMDATA31-
CMDATA0
(input)
4
2
Valid
3
H
PCLK
(input)
1
Figure 14. Control-Memory Interface – Read Operation



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