ThunderLAN

™ TNETE110A

PCI ETHERNET

™ CONTROLLER

SINGLE-CHIP 10 BASE-T

SPWS022A – APRIL 1996 – REVISED NOVEMBER 1996

20

POST OFFICE BOX 1443

switching characteristics, configuration EEPROM interface (see Figure 3 and Figure 8)

PARAMETER

MIN

MAX

UNIT

fCLK(EDCLK)

Clock frequency, EDCLK

0

100

kHz

td(EDCLKL-EDIOV)

EDCLK low to EDIO data in valid

0.3

3.5

µs

td(EDIO free)

Time the bus must be free before a new transmission can start

4.7

µs

td(EDIOV-EDCLKL)

Delay time, EDIO valid after EDCLK low (start condition hold time for EEPROM)

4

µs

tw(L)

Low period, clock

4.7

µs

tw(H)

High period, clock

4

µs

td(EDCLKH-EDIOV)

Delay time, EDCLK high to EDIO valid (start condition setup time)

4.7

µs

td(EDCLKL-EDIOX)

Delay time, EDCLK low to EDIO changing (data out hold time)

0

µs

td(EDIOV-EDCLKH)

Delay time, EDIO valid to EDCLK high (data out setup time)

250

ns

tr

Rise time, EDIO and EDCLK

1

µs

tf

Fall time, EDIO and EDCLK

300

ns

td(EDCLKH-EDIOH)

Delay time, EDCLK high to EDIO high (stop condition setup time)

4.7

µs

td(EDCLKL-EDIOX)

Delay time, EDCLK low to EDIO changing (data in hold time)

300

ns

td(EDCLKH-EDIOV)

EDCLK

EDIO (OUT)

EDIO (IN)

td(EDIOV-EDCLKL)

tf

td(EDCLKL-EDIOV)

tw(H)

tw(L)

td(EDCLKL-EDIOX)

td(EDIOV-EDCLKH)

td(EDCLKL-EDIOX)

tr

td(EDCLKH-EDIOH)

td(EDIO free)

Figure 8. Configuration EEPROM Interface Timing