M24LR64-R_12 datasheet(57/128 Pages) STMICROELECTRONICS

部品番号	M24LR64-R

部品情報	64 Kbit EEPROM with password protection & dual interface: 400 kHz I²C serial bus & ISO 15693 RF protocol at 13.56 MHz

PDF	128 Pages

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メーカー	STMICROELECTRONICS [STMicroelectronics]

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M24LR64-R

Data storage format identifier (DSFID)

Doc ID 15170 Rev 14

57/128

Data storage format identifier (DSFID)

The data storage format identifier indicates how the data is structured in the M24LR64-R

memory. The logical organization of data can be known instantly using the DSFID. It can be

programmed and locked using the Write DSFID and Lock DSFID commands.

15.1

CRC

The CRC used in the M24LR64-R is calculated as per the definition in ISO/IEC 13239. The

initial register contents are all ones: “FFFF”.

The two-byte CRC are appended to each request and response, within each frame, before

the EOF. The CRC is calculated on all the bytes after the SOF up to the CRC field.

Upon reception of a request from the VCD, the M24LR64-R verifies that the CRC value is

valid. If it is invalid, the M24LR64-R discards the frame and does not answer to the VCD.

Upon reception of a Response from the M24LR64-R, it is recommended that the VCD

verifies whether the CRC value is valid. If it is invalid, actions to be performed are left to the

discretion of the VCD designer.

The CRC is transmitted least significant byte first. Each byte is transmitted least significant

bit first.

Table 19.

CRC transmission rules

LSByte

MSByte

LSBit

MSBit

LSBit

MSBit

CRC 16 (8 bits)

M24LR64-R データシート(PDF) 57 Page - STMicroelectronics