WM8961 datasheet(86/116 Pages) WOLFSON

86 / 116 page

WM8961

Pre-Production

PP, August 2009, Rev 3.1

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R7 (07h)

Audio

Interface 0

ALRSWAP

Swaps L and R ADC data in interface

BCLKINV

BCLK invert bit (for master and slave modes)

0 : BCLK not inverted

1 : BCLK inverted

Master / Slave Mode Control

0 : Enable slave mode

1 : Enable master mode

DLRSWAP

Swap Left/Right channels on DAC path

LRP

Right, Left and I2S modes – LRC polarity

0 : normal LRC polarity

1 : invert LRC polarity

DSP Mode – mode A/B select

0 : MSB is available on 2

nd BCLK rising edge

after LRC rising edge (mode A)

1 : MSB is available on 1

st BCLK rising edge

after LRC rising edge (mode B)

3:2

WL[1:0]

Audio Interface Word Length

00 : 16 bit

01 : 20 bit

10 : 24 bit

11 : 32 bit

1:0

FORMAT[1:0]

Audio Interface Format

00: Right Justified

01: Left Justified

10: I2S

11: DSP

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R8 (08h)

Clocking2

8:6

DCLKDIV[2:0]

111

Class D switching clock divider.

000 = SYSCLK / 1

001 = SYSCLK / 2

010 = SYSCLK / 3

011 = SYSCLK / 4

100 = SYSCLK / 6

101 = SYSCLK / 8

110 = SYSCLK / 12

111 = SYSCLK / 16 (default for 12.288MHz/16 = 768 KHz)

(Note that Class D function further divides by 2 to run at 384 KHz)

CLK_SYS_ENA

Enable system clock. Power saving feature to gate clock to digital.

When this bit is enabled, an MCLK must be provided to allow access to

the control interface.

CLK_DSP_ENA

DSP clock enable. Power saving feature to gate clock to DSP while

allowing auxiliary functions to run

3:0

BCLKDIV[3:0]

0100

BCLK Frequency (Master Mode)

0000 = SYSCLK

0001 = Reserved

0010 = SYSCLK / 2

0011 = SYSCLK / 3

0100 = SYSCLK / 4 (default)

0101 = Reserved

0110 = SYSCLK / 6

0111 = SYSCLK / 8

WM8961 データシート(PDF) 86 Page - Wolfson Microelectronics plc

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