データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

Preview PDF HTML

ICX098AL データシート(PDF) 3 Page - Sony Corporation

部品番号 ICX098AL
部品情報  Diagonal 4.5mm (Type 1/4) Progressive Scan CCD Image Sensor with Square Pixel for B/W Cameras
PDF  21 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  SONY [Sony Corporation]
ホームページ  http://www.sony.co.jp
Logo SONY - Sony Corporation

ICX098AL データシート(HTML) 3 Page - Sony Corporation

  ICX098AL Datasheet HTML 1Page - Sony Corporation ICX098AL Datasheet HTML 2Page - Sony Corporation ICX098AL Datasheet HTML 3Page - Sony Corporation ICX098AL Datasheet HTML 4Page - Sony Corporation ICX098AL Datasheet HTML 5Page - Sony Corporation ICX098AL Datasheet HTML 6Page - Sony Corporation ICX098AL Datasheet HTML 7Page - Sony Corporation ICX098AL Datasheet HTML 8Page - Sony Corporation ICX098AL Datasheet HTML 9Page - Sony Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 3 / 21 page
background image
– 3 –
ICX098AL
Clock Voltage Conditions
Item
Readout clock voltage
VVT
VVH02A
VVH1, VVH2A,
VVH2B, VVH3
VVL1, VVL2A,
VVL2B, VVL3
V
φ1, Vφ2A,
V
φ2B, Vφ3
| VVL1 – VVL3 |
VVHH
VVHL
VVLH
VVLL
V
φH
VHL
V
φRG
VRGLH – VRGLL
VRGL – VRGLm
V
φSUB
14.55
–0.05
–0.2
–5.8
5.2
3.0
–0.05
3.0
19.75
15.0
0
0
–5.5
5.5
3.3
0
3.3
20.5
15.45
0.05
0.05
–5.2
5.8
0.1
0.3
1.0
0.5
0.5
5.25
0.05
5.5
0.4
0.5
21.25
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
1
2
2
2
2
2
2
2
2
2
3
3
4
4
4
5
VVH = VVH02A
VVL = (VVL1 + VVL3)/2
High-level coupling
High-level coupling
Low-level coupling
Low-level coupling
Low-level coupling
Low-level coupling
Horizontal transfer
clock voltage
Reset gate clock
voltage
Substrate clock voltage
Vertical transfer clock
voltage
Symbol
Min.
Typ.
Max.
Unit
Waveform
diagram
Remarks
Bias Conditions
Item
Supply voltage
Protective transistor bias
Substrate clock
Reset gate clock
VDD
VL
φSUB
φRG
14.55
15.0
∗1
∗2
∗2
15.45
V
Symbol
Min.
Typ.
Max.
Unit
Remarks
DC Characteristics
Item
Supply current
IDD
6.0
mA
Symbol
Min.
Typ.
Max.
Unit
Remarks
∗1 V
L
setting is the VVL voltage of the vertical transfer clock waveform, or the same power supply as the VL
power supply for the V driver should be used.
∗2 Do not apply a DC bias to the substrate clock and reset gate clock pins, because a DC bias is generated
within the CCD.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21


データシート ダウンロード

Go To PDF Page


リンク URL



ALLDATASHEETはお客様のビジネスに役立ちますか？  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   データシートへのリンク    |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com