Data Sheet

AS3588A

Rev. 3.1

Page 14 of 15

July 1999

Read Timing Characteristics (Continued): Operation over recommended temperature and voltage range

Symbol

Parameter

Condition

Min.

Typ.*

Max.

Units

tSCDRD

C/D Setup Time to Read

Pulse Start

20

ns

tHCDRD

C/D Hold Time from Read

PulseEnd

25

ns

tSASRD

Address Select Setup Time

to Read Pulse Start

20

ns

tHASRD

Address Select Hold Time

from Read Pulse End

25

ns

tPDD

Data Delay Time

CL = 200pF

120

ns

tHZ

Delay Time to High Z

80

ns

Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing

Note: Because of internal clock re-synchronization, one single additional requirement is recommended in order to produce a

simultaneous instruction flow in a multi-chip configuration: The RD rising edge has to be 20 to 20 + tWL(CK) ns late relative to

clock falling edge.

CS1, CS2

C/D

WR

RD

A1=S1

A2=S2

DOUT

tWLRD

tWHRD

tFRD

tRRD

tREPRD

tSHRD

tHHRD

tSLCSRD

tHLCSRD

tSHCSRD

tHHCSRD

tSCDRD

tHCDRD

tHZ

tSASRD

tHASRD

tPDD

Figure 7 Read Timing